Design of a Hybrid Column Segmented CMOS Image Sensor with an Artificial Intelligence Core and a Novel SRAM Readout Logic

Abstract

In this paper, a hybrid column segmented CMOS image sensor (CIS) with an artificial intelligence (AI) core and a novel SRAM readout circuit is presented. To obtain a high performance and high speed column parallel CIS, each column is segmented into two parts: the first one is a DC reference voltage generator with a bandgap reference circuit, and the second one is a fine ramp generator with an AI core and a digital-to-analog converter (DAC). Further, a novel SRAM readout circuit to improve the speed of digital block is also discussed. Based on this hybrid column segmented technique, excellent measured results are reported. With a 90nm backside illumination (BSI) technology, a 12-bit resolution image quality and 407uW power consumption per column are satisfied.