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More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recoveryopen access

Authors
Byun, Sangjin
Issue Date
Jun-2018
Publisher
MDPI
Keywords
linear phase detector; frequency detection capability; clock and data recovery; CMOS integrated circuits
Citation
ELECTRONICS, v.7, no.6
Indexed
SCIE
SCOPUS
Journal Title
ELECTRONICS
Volume
7
Number
6
URI
https://scholarworks.dongguk.edu/handle/sw.dongguk/9482
DOI
10.3390/electronics7060093
ISSN
2079-9292
Abstract
The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (f(DATA)) and the recovered clock frequency (f(CLK)) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of f(DATA) and f(CLK) is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.
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