A 5.8-17.6 GHz cascaded bi-directional distributed gain amplifier utilizing asymmetric stages in 65 nm CMOS

Abstract

A cascaded bidirectional distributed gain amplifier (BDGA) with asymmetrical stages has been reported. By cascading two unit BDGAs using a common source (CS) stage in the middle, the BDGA benefits the multiplicative gain enhancement while it can still achieve a wide bandwidth owing to the distributed nature of the two BDGAs. Each gain stage of the BDGA is composed of the CS output stage to enhance the linearity in parallel with the cascode input stage to improve noise performance by providing higher gain. The proposed circuit architecture is fabricated in a 65 nm CMOS. The measurements exhibit a gain of 10.5 dB, and the 3-dB bandwidth from 5.8 to 17.6 GHz. The measured output P1dB is 6.8 dBm along with 9.3 dBm of the saturated output power at 10 GHz. The circuit draws 75 mA from a 1.2 V supply and occupies 1.1 x 0.6 mm(2) of the chip area.