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An implementation of low latency address-mapping logic for SSD controllersopen access
- Issue Date
- 10-Nov-2019
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- SSD; FTL
- Citation
- IEICE ELECTRONICS EXPRESS, v.16, no.21, pp 1 - 6
- Pages
- 6
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 16
- Number
- 21
- Start Page
- 1
- End Page
- 6
- ISSN
- 1349-2543
- Abstract
- Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hard-wired to reduce the workload of the FTL inside an SSD.
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Related Researcher
- Hong, You Pyo
- College of Engineering (Department of Electronics and Electrical Engineering)