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An implementation of low latency address-mapping logic for SSD controllers
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Song, Yuchan | - |
| dc.contributor.author | So, Hyunjoo | - |
| dc.contributor.author | Chun, Yongjae | - |
| dc.contributor.author | Kim, Hyun-Seok | - |
| dc.contributor.author | Hong, Youpyo | - |
| dc.date.accessioned | 2023-04-28T01:40:57Z | - |
| dc.date.available | 2023-04-28T01:40:57Z | - |
| dc.date.issued | 2019-11-10 | - |
| dc.identifier.issn | 1349-2543 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/7408 | - |
| dc.description.abstract | Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hard-wired to reduce the workload of the FTL inside an SSD. | - |
| dc.format.extent | 6 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
| dc.title | An implementation of low latency address-mapping logic for SSD controllers | - |
| dc.type | Article | - |
| dc.publisher.location | 일본 | - |
| dc.identifier.doi | 10.1587/elex.16.20190521 | - |
| dc.identifier.scopusid | 2-s2.0-85076249523 | - |
| dc.identifier.wosid | 000498862900002 | - |
| dc.identifier.bibliographicCitation | IEICE ELECTRONICS EXPRESS, v.16, no.21, pp 1 - 6 | - |
| dc.citation.title | IEICE ELECTRONICS EXPRESS | - |
| dc.citation.volume | 16 | - |
| dc.citation.number | 21 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 6 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | Y | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | FLASH TRANSLATION LAYER | - |
| dc.subject.keywordPlus | MEMORY | - |
| dc.subject.keywordAuthor | SSD | - |
| dc.subject.keywordAuthor | FTL | - |
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Related Researcher
- Hong, You Pyo
- College of Engineering (Department of Electronics and Electrical Engineering)