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DRAM 고용량 커패시터 하부전극 제조방법Self-aligned stroage node electrode for DRAM cell and fabricating method thereof

Alternative Title
Self-aligned stroage node electrode for DRAM cell and fabricating method thereof
Authors
김삼동
URI
https://scholarworks.dongguk.edu/handle/sw.dongguk/60011
Abstract
본 발명은 티타늄 (Ti) 자기정렬 (Self-alignment) 방식을 통하여 제조된 티타늄 실리사이드 (TiSi2) 나노구조를 DRAM 커패시터의 하부전극으로 사용하여 고용량 커패시턴스를 구현하는 제조방법에 관한 것이다.
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College of Engineering > Department of Electronics and Electrical Engineering > 4. Patents
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