Etchant-Free Wafer-Scale 2D Transfer and van der Waals 3D Integration via Peel-Off Force Engineeringopen access
- Authors
- Pyo, Jinhyeok; Lim, Jungmoon; Byeon, Junsung; Park, Sohyeon; Kang, Sungsan; Park, Seonyou; Lee, Sung-Tae; Kim, Eunmin; Kim, Min Kyeong; Sohn, Jung Inn; Hong, John; Cho, Jungwan; Park, Kyung-Ho; Cha, Seungnam; Pak, Sangyeon
- Issue Date
- Jul-2025
- Publisher
- American Chemical Society
- Keywords
- TMDs; 2D transfer; surface tension; peel-off force; device integration
- Citation
- ACS Nano, v.19, no.28, pp 25860 - 25869
- Pages
- 10
- Indexed
- SCIE
SCOPUS
- Journal Title
- ACS Nano
- Volume
- 19
- Number
- 28
- Start Page
- 25860
- End Page
- 25869
- URI
- https://scholarworks.dongguk.edu/handle/sw.dongguk/58777
- DOI
- 10.1021/acsnano.5c04785
- ISSN
- 1936-0851
1936-086X
- Abstract
- Clean van der Waals (vdW) contacts are critical for realizing high-performance, reliable devices and integrated circuits based on two-dimensional (2D) transition metal dichalcogenides (TMDs). However, conventional transfer methods that rely on etchants often degrade TMDs, hampering the formation of pristine vdW interfaces. Here, we suggest an etchant-free transfer technique that prevents both direct and indirect damage by precisely controlling the peel-off force (POF) through surface-tension modulation (STM). Guided by a modified Kendall's model, we determine the optimal surface tension for common, nontoxic mixtures of deionized water and ethanol, thereby maximizing the POF. Using this POF-assisted method, we fabricate high-performance 2D vdW field-effect transistors (FETs), integrating device components without etchant-induced damage. These FETs exhibit a field-effect mobility of 162.2 cm2 <middle dot>V-1 <middle dot>s-1, an on/off ratio exceeding 108, a subthreshold swing of 72 mV<middle dot>dec-1, and an interface trap density of similar to 1012 cm-2<middle dot>eV-1, demonstrating high-quality vdW contacts. Finally, we suggest the all-vdW logic circuit design, demonstrated through a complementary metal-oxide-semiconductor (CMOS) logic test structure. This work demonstrates a process-compatible approach for the lab-to-fab transition of 2D TMD electronics, achieving reliable device yields and the performance levels required for next-generation vdW-integrated systems.
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Collections - College of Natural Science > Department of Physics > 1. Journal Articles

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