A High Performance 32X32-bit Multiplier Using Pass-Gate Combined CMOS Logic

송민규

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A High Performance 32X32-bit Multiplier Using Pass-Gate Combined CMOS Logic

Authors: 송민규

Issue Date: 24-Feb-2000

URI: https://scholarworks.dongguk.edu/handle/sw.dongguk/37484

Place: 대한민국
KAIST/대전

Conference Date: 2000-02-24 ~ 2000-02-25

Conference Name: IDEC Conference 2000

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Appears in Collections: College of Advanced Convergence Engineering > Division of System Semiconductor > 2. Conference Papers

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Song, Min Kyu: College of Advanced Convergence Engineering (Division of System Semiconductor)

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