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Cited 70 time in webofscience Cited 71 time in scopus
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Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformityopen access

Authors
Kim, TaikyuChoi, Cheol HeeByeon, PilgyuLee, MisoSong, AeranChung, Kwun-BumHan, SeungwuChung, Sung-YoonPark, Kwon-ShikJeong, Jae Kyeong
Issue Date
Jan-2022
Publisher
NATURE PUBLISHING GROUP
Keywords
Alumina; Aluminum Oxide; Field Effect Transistors; Film Growth; Gallium Compounds; Metals; Mos Devices; Oxide Semiconductors; Physical Vapor Deposition; Silica; Silicon Wafers; Tellurium Compounds; Zinc Compounds; Field-effect Transistor; High Mobility; High Quality; P Channels; P Type Semiconductor; P-channel Field Effect Transistors; Performance; Physical Vapour Deposition; Telluria Film; Wafer Scale; Cmos Integrated Circuits
Citation
npj 2D Materials and Applications, v.6, no.1
Indexed
SCIE
SCOPUS
Journal Title
npj 2D Materials and Applications
Volume
6
Number
1
URI
https://scholarworks.dongguk.edu/handle/sw.dongguk/3708
DOI
10.1038/s41699-021-00280-7
ISSN
2397-7132
2397-7132
Abstract
Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm(2) V-1 s(-1) and an I-ON/OFF ratio of 5.8 x 10(5) with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of similar to 75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.
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