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Design of a High Speed CMOS Image Sensor with a Hybrid Single-Slope Column ADC and a Finite State Machine
- Authors
- Park, Keunyeol; Jin, Minhyun; Kim, Soo Youn; Song, Minkyu
- Issue Date
- 29-May-2018
- Publisher
- IEEE
- Keywords
- CMOS image sensor; hybrid single-slope column ADC; sampling capacitor; single ramp generator; 4-input comparator; finite state machine
- Citation
- PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017), pp 95 - 96
- Pages
- 2
- Indexed
- SCOPUS
- Journal Title
- PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017)
- Start Page
- 95
- End Page
- 96
- ISSN
- 2163-9612
- Abstract
- In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 x 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).
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Related Researcher
- Song, Min Kyu
- College of Advanced Convergence Engineering (Division of System Semiconductor)