Design of an Asynchronous Detector with Priority Encoding Technique
- Authors
- Park, K.; Kwon, O.; Noh, H.; Jin, M.; Song, M.
- Issue Date
- 20-Jul-2017
- Publisher
- IEEE Computer Society
- Keywords
- asynchronous detector; CMOS process; priority encoding technique
- Citation
- Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, v.2017-July, pp 529 - 532
- Pages
- 4
- Indexed
- SCOPUS
- Journal Title
- Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
- Volume
- 2017-July
- Start Page
- 529
- End Page
- 532
- URI
- https://scholarworks.dongguk.edu/handle/sw.dongguk/25216
- DOI
- 10.1109/ISVLSI.2017.98
- ISSN
- 2159-3469
- Abstract
- This paper presents an asynchronous detector with priority encoding technique. Conventionally, a normal synchronous detector like an image sensor checks all the outputs of detection cells, whatever the cells are activated or not. Thus, it spends a lot of undesired power consumption. On the contrary, an asynchronous detector to only check the activated cells has a small power consumption, even though it has a low operating speed. In order to improve the data transfer rates, a priority encoding technique is described. A test chip to verify the proposed technique has fabricated with 3.3V 0.18um 1-poly 5-metal CMOS process. The effective chip area is 0.345 mm2 and power consumption is about 8mW. The measured performance shows 65,026 patterns. © 2017 IEEE.
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Collections - College of Advanced Convergence Engineering > Division of System Semiconductor > 1. Journal Articles

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