A Low Noise CMOS Image Sensor with a 14-bit Two-Step Single-Slope ADC and a Column Self-Calibration Technique

Abstract

In this paper, a low-noise CMOS Image Sensor (CIS) based on a 14-bit Two-Step Single-Slope ADC (TS SS ADC) and a column self-calibration technique is proposed. The TS SS ADC is good for the video system which requires fast operation because its conversion speed is faster than the Single Slope ADC (SS ADC) by more than 10 times. However, there are a lot of errors in the circuit operation on the connection point between the coarse block and the fine block due to the 2-step composition of the TS SS ADC. This makes it difficult to implement the TS SS ADC into the high resolution more than 10-bit and the product. In order to improve the drawbacks of TS SS ADC, a new 4-input comparator is discussed. Further, a column self-calibration technique to reduce the Fixed Pattern Noise (FPN) is also described. The chip has been fabricated by Samsung 0.13 mu m CIS technology. The measured conversion time of the ADC is 17 mu s and the high frame rate of 120 frames/s (fps) is achieved at the VGA resolution. The measured column FPN is 0.38LSB, and it is much lower than the other reported ones.