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Design of a 9-bit 1GS/s CMOS Folding A/D Converter with a Boundary Error Reduction Technique
- Issue Date
- 5-Nov-2014
- Publisher
- IEEE
- Keywords
- CMOS folding ADC; boundary error reduction technique; enhanced digital architecture
- Citation
- 2014 27TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC), pp 82 - 87
- Pages
- 6
- Indexed
- SCOPUS
- Start Page
- 82
- End Page
- 87
- ISSN
- 2164-1676
2164-1706
- Abstract
- In this paper, design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique is described. In order to reduce the asymmetrical boundary error of the folding ADCs, a new circuit is proposed. Further, an enhanced digital architecture is discussed to support the boundary error reduction technique. The fabricated ADC has a novel digital logic to minimize device mismatching and many errors. The chip has been implemented with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99mm(2) and the power dissipation is 120mW. The measured result of SNDR is 45.35dB, when the input frequency is 150MHz at the sampling frequency of 1GHz. The measured INL is within +5LSB/-3LSB and DNL is within +1.5LSB/-1LSB
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Related Researcher
- Song, Min Kyu
- College of Advanced Convergence Engineering (Division of System Semiconductor)