A Low Power Priority Encoding Technique with Address-Encoder and Reset-Decoder for an Improved Hierarchical Asynchronous Detector

Abstract

A novel priority encoding technique with an address-encoder and reset-decoder(AERD) for a hierarchical asynchronous detector is discussed. Conventionally, an asynchronous detector has a slow operating speed, because it checks and takes the only activated cells. In order to enhance the data transfer rates, an improved hierarchical asynchronous detector is proposed. Further, a low power priority encoding technique with an AERD is also described. A test chip to verify the proposed technique has been fabricated with a Hynix 0.18um CMOS technology. The power consumption is about 7.5mW, which is much smaller than the conventional ones at the same patterns.