Cited 2 time in
A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choe, Young-Joe | - |
| dc.contributor.author | Nam, Hyohyun | - |
| dc.contributor.author | Park, Jung-Dong | - |
| dc.date.accessioned | 2023-04-28T02:41:07Z | - |
| dc.date.available | 2023-04-28T02:41:07Z | - |
| dc.date.issued | 2019-09 | - |
| dc.identifier.issn | 2079-9292 | - |
| dc.identifier.issn | 2079-9292 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/7729 | - |
| dc.description.abstract | We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push-pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Omega load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm(2) without pads. | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | MDPI | - |
| dc.title | A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology | - |
| dc.type | Article | - |
| dc.publisher.location | 스위스 | - |
| dc.identifier.doi | 10.3390/electronics8091043 | - |
| dc.identifier.scopusid | 2-s2.0-85073431469 | - |
| dc.identifier.wosid | 000489128400130 | - |
| dc.identifier.bibliographicCitation | ELECTRONICS, v.8, no.9 | - |
| dc.citation.title | ELECTRONICS | - |
| dc.citation.volume | 8 | - |
| dc.citation.number | 9 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | Y | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | DESIGN | - |
| dc.subject.keywordAuthor | CMOS | - |
| dc.subject.keywordAuthor | power amplifier | - |
| dc.subject.keywordAuthor | power supply rejection ratio | - |
| dc.subject.keywordAuthor | wireless | - |
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