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Low-power column counter with a logical-shift algorithm for CMOS image sensors
- Authors
- Park, K.; Kim, S. Y.
- Issue Date
- 5-Mar-2020
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- analogue-digital conversion; low-power electronics; CMOS image sensors; low-power column counter; logical-shift algorithm; column-parallel single-slope ADC; low-power CMOS image sensors; power consumption; internal toggling nodes; power-delay product; parasitic capacitance
- Citation
- ELECTRONICS LETTERS, v.56, no.5, pp 232 - 234
- Pages
- 3
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 56
- Number
- 5
- Start Page
- 232
- End Page
- 234
- ISSN
- 0013-5194
1350-911X
- Abstract
- The authors propose a column counter that uses a logical-shift algorithm in column-parallel single-slope ADCs for low-power CMOS image sensors. The proposed column counter lowers power consumption by reducing the amount of internal toggling nodes and parasitic capacitance. Simulation results showed a 32% reduction in power consumption and a 60% reduction in the power-delay product compared to a conventional up/down counter.
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Related Researcher
- Kim, Soo Youn
- College of Advanced Convergence Engineering (Division of System Semiconductor)