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Low-power column counter with a logical-shift algorithm for CMOS image sensors
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, K. | - |
| dc.contributor.author | Kim, S. Y. | - |
| dc.date.accessioned | 2023-04-27T23:40:57Z | - |
| dc.date.available | 2023-04-27T23:40:57Z | - |
| dc.date.issued | 2020-03-05 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.issn | 1350-911X | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/6792 | - |
| dc.description.abstract | The authors propose a column counter that uses a logical-shift algorithm in column-parallel single-slope ADCs for low-power CMOS image sensors. The proposed column counter lowers power consumption by reducing the amount of internal toggling nodes and parasitic capacitance. Simulation results showed a 32% reduction in power consumption and a 60% reduction in the power-delay product compared to a conventional up/down counter. | - |
| dc.format.extent | 3 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
| dc.title | Low-power column counter with a logical-shift algorithm for CMOS image sensors | - |
| dc.type | Article | - |
| dc.publisher.location | 영국 | - |
| dc.identifier.doi | 10.1049/el.2019.2496 | - |
| dc.identifier.scopusid | 2-s2.0-85085729437 | - |
| dc.identifier.wosid | 000519133900009 | - |
| dc.identifier.bibliographicCitation | ELECTRONICS LETTERS, v.56, no.5, pp 232 - 234 | - |
| dc.citation.title | ELECTRONICS LETTERS | - |
| dc.citation.volume | 56 | - |
| dc.citation.number | 5 | - |
| dc.citation.startPage | 232 | - |
| dc.citation.endPage | 234 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordAuthor | analogue-digital conversion | - |
| dc.subject.keywordAuthor | low-power electronics | - |
| dc.subject.keywordAuthor | CMOS image sensors | - |
| dc.subject.keywordAuthor | low-power column counter | - |
| dc.subject.keywordAuthor | logical-shift algorithm | - |
| dc.subject.keywordAuthor | column-parallel single-slope ADC | - |
| dc.subject.keywordAuthor | low-power CMOS image sensors | - |
| dc.subject.keywordAuthor | power consumption | - |
| dc.subject.keywordAuthor | internal toggling nodes | - |
| dc.subject.keywordAuthor | power-delay product | - |
| dc.subject.keywordAuthor | parasitic capacitance | - |
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Related Researcher
- Kim, Soo Youn
- College of Advanced Convergence Engineering (Division of System Semiconductor)