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Multilevel Switching Characteristics of Si3N4-Based Nano-Wedge Resistive Switching Memory and Array Simulation for In-Memory Computing Application

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dc.contributor.authorLee, Dong Keun-
dc.contributor.authorKim, Min-Hwi-
dc.contributor.authorBang, Suhyun-
dc.contributor.authorKim, Tae-Hyeon-
dc.contributor.authorKim, Sungjun-
dc.contributor.authorCho, Seongjae-
dc.contributor.authorPark, Byung-Gook-
dc.date.accessioned2023-04-27T22:40:38Z-
dc.date.available2023-04-27T22:40:38Z-
dc.date.issued2020-08-
dc.identifier.issn2079-9292-
dc.identifier.issn2079-9292-
dc.identifier.urihttps://scholarworks.dongguk.edu/handle/sw.dongguk/6372-
dc.description.abstractIn this research, nano-wedge resistive switching random-access memory (ReRAM) based on a Si(3)N(4)switching layer and silicon bottom electrode was fabricated, and its multilevel switching characteristics were investigated. The wedge bottom electrode was formed by a tetramethyl ammonium hydroxide (TMAH) wet-etching process. The nano-wedge ReRAM was demonstrated to have different reset current levels by varying the compliance currents. To explain the effect of modulating the compliance currents, the switching characteristics of both the SET and RESET behaviors were shown. After measuring the device under four different compliance currents, it was proved to have different current levels due to an inhibited resistive state after a SET switching process. Furthermore, SPICE circuit simulation was carried out to show the effect of line resistance on current summation for the array sizes of 8 x 8 and 16 x 16. These results indicate the importance of minimizing the line resistance for successful implementation as a hardware-based neural network.-
dc.format.extent8-
dc.language영어-
dc.language.isoENG-
dc.publisherMDPI-
dc.titleMultilevel Switching Characteristics of Si3N4-Based Nano-Wedge Resistive Switching Memory and Array Simulation for In-Memory Computing Application-
dc.typeArticle-
dc.publisher.location스위스-
dc.identifier.doi10.3390/electronics9081228-
dc.identifier.scopusid2-s2.0-85088933137-
dc.identifier.wosid000567150900001-
dc.identifier.bibliographicCitationELECTRONICS, v.9, no.8, pp 1 - 8-
dc.citation.titleELECTRONICS-
dc.citation.volume9-
dc.citation.number8-
dc.citation.startPage1-
dc.citation.endPage8-
dc.type.docTypeArticle-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusRESET MECHANISM-
dc.subject.keywordPlusSYNAPSE DEVICE-
dc.subject.keywordPlusCONDUCTANCE-
dc.subject.keywordAuthornano-wedge-
dc.subject.keywordAuthorresistive switching random-access memory-
dc.subject.keywordAuthorswitching layer-
dc.subject.keywordAuthorTMAH-
dc.subject.keywordAuthorswitching process-
dc.subject.keywordAuthorarray-
dc.subject.keywordAuthorneural network-
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