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산화막 기둥을 포함한 수직방향 트랜지스터 기반 2T DRAM 셀
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김수연 | - |
| dc.contributor.author | 공성환 | - |
| dc.contributor.author | 심원보 | - |
| dc.date.accessioned | 2025-11-29T04:30:17Z | - |
| dc.date.available | 2025-11-29T04:30:17Z | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/62200 | - |
| dc.title | 산화막 기둥을 포함한 수직방향 트랜지스터 기반 2T DRAM 셀 | - |
| dc.title.alternative | 2T DRAM cell with vertical transistor having oxide pillar | - |
| dc.type | Patent | - |
| dc.publisher.location | 대한민국 | - |
| dc.contributor.assignee | 동국대학교산학협력단;서울과학기술대학교 산학협력단 | - |
| dc.date.application | 2024-05-31 | - |
| dc.date.registration | 2025-11-06 | - |
| dc.type.iprs | 특허 | - |
| dc.identifier.patentRegistrationNumber | 10-2884514 | - |
| dc.identifier.patentApplicationNumber | 10-2024-0071309 | - |
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Related Researcher
- Kim, Soo Youn
- College of Advanced Convergence Engineering (Division of System Semiconductor)