Array-Integrated Memristor with an Interference-Suppressed Pulse Scheme for Multibit Neuromorphic and Edge Computing

Abstract

In this study, we developed a Pt/Al/TiO y /TiO x /HfO2/Pt memristor device featuring an optimized annealing process and an integrated TiO y overshoot layer to mitigate current overshoot during electroforming, achieving current-compliant-free and forming-free features. Extensive characterization demonstrated stable resistive switching properties, including a high on/off ratio (similar to 10), reliable retention, and endurance across a 24 x 24 crossbar array. Multilevel cell operation enabled precise programming, achieving up to 6-bit levels through the Incremental Step Pulse with Verify Algorithm (ISPVA) method. The device's synaptic potential was further evaluated using the Extended Modified National Institute of Standards and Technology (EMNIST) data set. ISPVA-based training achieved superior classification accuracy of 92.6% for a subset (N = 6) and 83.34% for the full alphabet (N = 26), outperforming conventional incremental pulse methods. Furthermore, resistive switching voltage range-based program sequencing makes weight transfer accurate. These findings highlight the Pt/Al/TiO y /TiO x /HfO2/Pt memristor as a core synaptic element for scalable, high-density, and energy-efficient neuromorphic computing systems.