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IoT 가상기계의 중간코드 검증을 위한 RSIL to LLVM IR 변환기의 설계 및 구현
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 손윤식 | - |
| dc.date.accessioned | 2024-10-30T20:04:12Z | - |
| dc.date.available | 2024-10-30T20:04:12Z | - |
| dc.date.issued | 2017-04-28 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/54304 | - |
| dc.title | IoT 가상기계의 중간코드 검증을 위한 RSIL to LLVM IR 변환기의 설계 및 구현 | - |
| dc.type | Conference | - |
| dc.citation.startPage | 1135 | - |
| dc.citation.endPage | 1137 | - |
| dc.citation.conferenceName | 한국정보처리학회 2017년 춘계학술발표대회 | - |
| dc.citation.conferencePlace | 대한민국 | - |
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Related Researcher
- Son, Yun Sik
- College of Advanced Convergence Engineering (Department of Computer Science and Artificial Intelligence)