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Design of a 9-bit 1GS/s CMOS Folding A/D Converter with a Boundary Error Reduction Technique

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dc.contributor.author송민규-
dc.date.accessioned2024-10-30T15:23:15Z-
dc.date.available2024-10-30T15:23:15Z-
dc.date.issued2014-09-03-
dc.identifier.urihttps://scholarworks.dongguk.edu/handle/sw.dongguk/50100-
dc.titleDesign of a 9-bit 1GS/s CMOS Folding A/D Converter with a Boundary Error Reduction Technique-
dc.typeConference-
dc.citation.startPage83-
dc.citation.endPage87-
dc.citation.conferenceNameIEEE International SOC Conference(SOCC 2014)-
dc.citation.conferencePlace미국-
dc.citation.conferencePlace미국 라스베가스-
dc.citation.conferenceDate2014-09-01 ~ 2014-09-04-
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College of Advanced Convergence Engineering > Division of System Semiconductor > 2. Conference Papers

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