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A 1.8V 6-bit 1GS/s 60mW CMOS Folding/Interpolation ADC Using Folder Reduction Circuit and Auto Switching Encoder
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 송민규 | - |
| dc.date.accessioned | 2024-10-30T05:22:03Z | - |
| dc.date.available | 2024-10-30T05:22:03Z | - |
| dc.date.issued | 2008-09-02 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/41201 | - |
| dc.title | A 1.8V 6-bit 1GS/s 60mW CMOS Folding/Interpolation ADC Using Folder Reduction Circuit and Auto Switching Encoder | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | IEEE Conference on Electronics, Circuits, and Systems (ICECS'08) | - |
| dc.citation.conferencePlace | 몰타 | - |
| dc.citation.conferencePlace | 몰타 | - |
| dc.citation.conferenceDate | 2008-08-31 ~ 2008-09-03 | - |
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Related Researcher
- Song, Min Kyu
- College of Advanced Convergence Engineering (Division of System Semiconductor)