A New CMOS Ultra Low Power Flip-Flop Circuit with a Minimization of Internal Node Transitions

Abstract

In this paper, a new CMOS ultra low power flip-flop (ULPFF) circuit with a minimization technique of internal node transitions is discussed. In order to reduce power consumption, a new technique to eliminate short-circuit currents is also proposed. The proposed ULPFF is composed of 24 CMOS transistors, and it has the lowest power consumption among other conventional FFs. From the measured results with a 65 nm CMOS process, the power consumption of proposed ULPFF is reduced by 90% at the data activity ratio of 0% and by 30% at the data activity of 100%, respectively, compared to those of conventional transmission gate FF(TGFF)