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패스트랜지스터 로직을 이용한 저전력 고속 54 X 54-bit 곱셈기
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 송민규 | - |
| dc.date.accessioned | 2024-10-30T03:11:23Z | - |
| dc.date.available | 2024-10-30T03:11:23Z | - |
| dc.date.issued | 1999-05-08 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/38142 | - |
| dc.title | 패스트랜지스터 로직을 이용한 저전력 고속 54 X 54-bit 곱셈기 | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | 1999년도 대한전자공학회 CAD 및 VLSI 설계연구회 학술발표대회 | - |
| dc.citation.conferencePlace | 대한민국 | - |
| dc.citation.conferencePlace | 성균관대(수원) | - |
| dc.citation.conferenceDate | 1999-05-08 | - |
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Related Researcher
- Song, Min Kyu
- College of Advanced Convergence Engineering (Division of System Semiconductor)