Design of a CMOS Image Sensor with a 10-bit Two-Step Single-Slope A/D Converter and a Hybrid Correlated Double Sampling

Abstract

In this paper, a low-noise CMOS Image Sensor (CIS) based on a 10-bit two-step Single Slope A/D Converter (SS-ADC) with Hybrid CDS is proposed. In order to reduce the pixel noise, a Hybrid Correlated Double Sampling (H-CDS) is discussed. With this technique, Column Fixed Pattern Noise (CFPN) is drastically reduced by about 55% or more, compared to that of analog CDS only. Furthermore, to overcome low conversion speed of SS-ADC, two-step SS-ADC is proposed. The conversion speed of proposed two-step SS-ADC is 5us, while that of the conventional SS-ADC is about 40us at 25MHz reference clock. The proposed CIS has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320x240) resolution. The fabricated chip size is 5mm x 3mm, and the power consumption is about 35mW at 3.3V supply voltage. The measured CFPN is 0.8LSB, and the frame rate is 220 frames/s.