A High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

Abstract

A high precision CMOS folding A/D Converter(ADC) with an odd number of folding blocks is described. In order to improve the performance of normal folding types with an even number of folding blocks, a new scheme is proposed. A novel digital encoder, a digital error correction logic, and a self-calibration technique are discussed. To verify the proposed technique, an 8-bit folding ADC is designed with a 0.13um CMOS process at 1.2V power supply. The measured values of INL and DNL are within 0.5LSB, respectively, and the measured SNDR is about 46dB at the conversion rate of 1GS/s.