Design of a High-speed CMOS Image Sensor with an Intelligent Digital Correlated Double Sampling and a Symmetrical 3-Input Comparator

Abstract

In order to improve the frame rate of a CMOS image sensor (CIS), a novel technique of correlated double sampling (CDS) and a symmetrical 3-input comparator are discussed. In the conventional digital CDS, a subtraction algorithm between the reset digital code and the pixel digital code has been normally adopted. Thus, it needs two ramps and takes a much more operating time, compared to that of analog CDS. In this paper, an intelligent digital CDS is proposed drastically to reduce the operating time. Further, a symmetrical 3-input comparator to implement the intelligent digital CDS is also described. A high speed CIS with the proposed CDS and a symmetrical 3-input comparator has been fabricated with Samsung 0.13um CIS technology. A high frame rate of 240fps is achieved at the VGA resolution of 640x480 with 39mW power consumption.