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Cited 10 time in webofscience Cited 11 time in scopus
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A 400 Mb/s ~ 2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

Authors
Byun, Sangjin
Issue Date
Oct-2016
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Clock and data recovery; CMOS integrated circuits; frequency detection; linear phase detector
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.10, pp 1592 - 1604
Pages
13
Indexed
SCI
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume
63
Number
10
Start Page
1592
End Page
1604
URI
https://scholarworks.dongguk.edu/handle/sw.dongguk/23404
DOI
10.1109/TCSI.2016.2587751
ISSN
1549-8328
1558-0806
Abstract
A 400 Mb/s similar to 2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 mu m CMOS process. With 2.5 Gb/s, 2(31) - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 mu s, the bit error rate (BER) is better than 10(-12), the jitter of the recovered clock is 8.6 ps(rms) and the out-of-band jitter tolerance is 0.32 UIpp.
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