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A 400 Mb/s ~ 2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Byun, Sangjin | - |
| dc.date.accessioned | 2024-09-25T03:00:26Z | - |
| dc.date.available | 2024-09-25T03:00:26Z | - |
| dc.date.issued | 2016-10 | - |
| dc.identifier.issn | 1549-8328 | - |
| dc.identifier.issn | 1558-0806 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/23404 | - |
| dc.description.abstract | A 400 Mb/s similar to 2.5 Gb/s referenceless clock and data recovery (CDR) IC is presented. This paper shows that the half-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability in itself. By using this intrinsic frequency detection capability of the half-rate linear PD, a CDR can be implemented in the single loop architecture without both an external reference clock and a separate frequency detector. For verification, a prototype CDR IC was fabricated in a 0.13 mu m CMOS process. With 2.5 Gb/s, 2(31) - 1 pseudorandom binary sequence (PRBS), the measurement results show that the frequency acquisition time is 17 mu s, the bit error rate (BER) is better than 10(-12), the jitter of the recovered clock is 8.6 ps(rms) and the out-of-band jitter tolerance is 0.32 UIpp. | - |
| dc.format.extent | 13 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | A 400 Mb/s ~ 2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/TCSI.2016.2587751 | - |
| dc.identifier.scopusid | 2-s2.0-85027581965 | - |
| dc.identifier.wosid | 000385621800004 | - |
| dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.10, pp 1592 - 1604 | - |
| dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
| dc.citation.volume | 63 | - |
| dc.citation.number | 10 | - |
| dc.citation.startPage | 1592 | - |
| dc.citation.endPage | 1604 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | sci | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordPlus | 65 NM CMOS | - |
| dc.subject.keywordPlus | RECOVERY CIRCUIT | - |
| dc.subject.keywordPlus | REFERENCE CLOCK | - |
| dc.subject.keywordPlus | ACQUISITION | - |
| dc.subject.keywordPlus | TRANSCEIVER | - |
| dc.subject.keywordAuthor | Clock and data recovery | - |
| dc.subject.keywordAuthor | CMOS integrated circuits | - |
| dc.subject.keywordAuthor | frequency detection | - |
| dc.subject.keywordAuthor | linear phase detector | - |
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