Perhydropolysilazane spin-on dielectrics for inter-layer-dielectric applications of sub-30 nm silicon technology

Abstract

Various material properties of the perhydropolysilazane spin-on dielectric (PHPS SOD) were examined and analyzed in this study as potential inter-layer dielectrics (ILDs) integrated for Si circuits of 30 nm technology or beyond. The spin-coated PHPS (18.5 wt%) layers converted at 650 degrees C showed comparable but less perfect thermal conversion to silica than the films converted at 1000 degrees C, however exhibiting excellent gap filling (15 nm gap opening, aspect ratio (AR) of similar to 23) and planarization (degree of planarization (DOP)= similar to 73% for 800 nm initial step height, cusp angle = similar to 16 degrees) sufficient for the Si integration. PHPS SOD layers cured at 650 degrees C were integrated ILDs in the 0.18 mu m Si front-end-of-the-line process, and the estimated hot-carrier reliability of n-channel metal oxide semiconductor transistors (ten years at a drain voltage of 1.68 V) had no significant difference from that of the transistors integrated with the conventional borophosposilicate glass ILDs. A modified contact pre-cleaning scheme using N2O plasma treatment also produced uniform and stable contact chain resistances from the SOD ILDs.