Low-Complexity Residual-Corrected Loss-Minimization Current-Reference Generation for PMSM Drives

초록

This paper proposes a low-complexity residual-corrected loss-minimization current-reference generation method for permanent magnet synchronous motor (PMSM) drives. Existing loss-minimization control (LMC) methods often rely on lookup tables, numerical optimization, high-order algebraic equations, or explicit approximations based on maximum torque per ampere (MTPA) and maximum torque per voltage (MTPV) references. While effective, these simplified approximations often introduce residual errors relative to the true loss-optimal conditions. To address this, this paper adopts a more consistent iron-loss equivalent-circuit objective and analytically eliminates the torque equality constraint, reducing the LMC problem to a one-dimensional scalar minimization problem of the d-axis current. This paper demonstrates that this reduced objective is strictly convex over the admissible scalar domain, allowing for an exact benchmark solution via a scalar convex solver. The proposed method constructs a resistance-aware initial reference from explicit MTPA and MTPV approximations and then applies a one-step scalar Newton-type residual correction using the gradient and Hessian of the reduced loss objective. The initial reference reproduces the known exact surface-mounted PMSM (SPMSM) LMC solution in the SPMSM limit. The correction direction is proved to be a strict descent direction, and a safeguarded step-size ensures loss reduction compared to the initial approximation. The main novelty is the use of the scalar LMC optimality residual as a fixed-cost correction layer for explicit LMC references. The numerical validation is interpreted as steady-state current-reference mapping accuracy and model-based controllable loss-objective verification against the exact scalar optimum, not as hardware drive-efficiency validation. Tests including the no-MTPV case show reduced current-reference and loss-objective gaps while retaining a fixed-cost structure that may support future embedded implementation after validation; hardware transient and efficiency validation under inverter nonlinearity, temperature variation, saturation, and PWM effects remains for future work.

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