A Compute-in-Memory Based on Approximate Multiplication with a Calibration Adder

초록

This paper presents an energy-efficient compute-in-memory (CIM) architecture with approximated multiplication and a calibration adder. The proposed CIM applies Mitchell's approximate multiplication to implement multiply-accumulate (MAC) with a single addition operation for multiplication, regardless of input precision, thereby reducing both latency and power consumption of arithmetic operations. Furthermore, the precision degradation caused by approximate multiplication can be improved by approximately 3.4% on average using the proposed calibration adder (C-Adder). Each computing element utilizes an 8T-SRAM-based structure with separate local and global read bit lines to enable parallel MAC operations and further enhance computational throughput. Implemented in a 28-nm CMOS process, the proposed CIM achieves 38.65 TOPS/W energy efficiency, 0.05003 TOPS/mm2 area efficiency, and 91.86 % inference accuracy on ResNet-20 with CIFAR-10. © 2026 IEEE.

키워드