초록
We present an efficient method of enhancing the harmonic rejection ratio (HRR) of a millimeter-wave frequency multiplier (FM) by utilizing optimal capacitive loads with minimal area overheads. To verify the proposed method, we demonstrate an eight-times FM ( × 8 FM) with an HRR of 35–50 dBc over a wideband of 20.8 GHz from 70.4 to 91.2 GHz in the 65-nm CMOS technology. The designed × 8 FM comprises three stages of push–push doublers (PPDs), and each PPD is followed by a driving amplifier (DA) to suppress undesirable spurs and provide optimal power levels. The transformer (TF)-based baluns in each PPD are rebalanced using two separate capacitive loads connected to the output terminals of the TF. The proposed technique achieves more than 10 dB of improvement in the HRR for the entire FM chain with a significant bandwidth enhancement in simulation. The fabricated × 8 FM achieves a peak output power of 6.3 dBm at 78.16 GHz with a dc current of 164 mA from a 1.2-V supply voltage. The chip area is 0.95 mm 2 , including the pads, whereas the core layout area is only 0.35 mm 2 . IEEE