Compute-in-Memory with SAR ADC and 2T1C DRAM for MAC Operations

초록

This paper presents a compute-in-memory (CIM) architecture for MAC operation using 2T1 C dynamic random access memory (DRAM) and a successive-approximation analog-to-digital converter (SAR ADC). The proposed design features CIM analog multiplication and summation architecture consisting of a digital-to-time converter (DTC) and SAR ADC. The DTC converts the input code into clock-based pulse width, and the calculation can be done by passing through pulse into a 2T1C DRAM array in parallel. The proposed structure is implemented using a 28-nm CMOS process, operates four parallel 2-bit× 4-bit multiplication and total summation simultaneously, and a single calculation requires 140ns for 100MHz system clock frequency. © 2024 IEEE.

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