Low-Power On-Chip Calibration System for Spiking Neural Networks

초록

This paper presents a low-power spiking neural network (SNN) system enabling on-chip calibration with pulse-driven computation (PDC) for weight update based on the delta rule algorithm. During the calibration phase, the proposed PDC scheme computes delta weights without multipliers, thereby avoiding memory access overhead. By converting error values and input spikes into pulse-width and frequency signals, respectively, the proposed calibration architecture implements weight updates via simple pulse counting using counters and logic gates. Additionally, a weak softmax approximation and input scaling method are employed to reduce bit-width and maintain accuracy. The proposed SNN system, fabricated in a 28 nm CMOS technology, achieves an inference energy efficiency of 0.2 pJ/SOP and a calibration efficiency of 3.25 TOPS/W. Measurements on the MNIST dataset confirm that the proposed SNN system effectively compensates for process variations across multiple chips, achieving an accuracy improvement of 17-37% and a power reduction of 95-99% compared to conventional multiplier-based MAC designs.

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