A vertical WSe2-MoSe2 p-n heterostructure with tunable gate rectification

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초록

Here, we report the synthesis of a vertical MoSe2/WSe2 p-n heterostructure using a sputtering-CVD method. Unlike the conventional CVD method, this method produced a continuous MoSe2/WSe2 p-n heterostructure. WSe2 and MoSe2 back-gated field effect transistors (FETs) exhibited good gate modulation behavior, and high hole and electron mobilities of approximate to 2.2 and approximate to 15.1 cm(2) V-1 s(-1), respectively. The fabricated vertical MoSe2/WSe2 p-n diode showed rectifying I-V behavior with back-gate tunability. The rectification ratio of the diode was increased with increasing gate voltage, and was increased from approximate to 18 to approximate to 1600 as the gate bias increased from -40 V to +40 V. This is attributed to the fact that the barrier height between p-WSe2 and n-MoSe2 is modulated due to the back-gate bias. The rectification ratio is higher than the previously reported values for the TMDC p-n heterostructure grown by CVD.

키워드

CHEMICAL-VAPOR-DEPOSITIONLARGE-AREA SYNTHESISATOMIC LAYERSMOS2WSE2MONOLAYERGROWTHFILMS
제목
A vertical WSe2-MoSe2 p-n heterostructure with tunable gate rectification
저자
Liu, HailingHussain, SajjadAli, AsifNaqvi, Bilal AbbasVikraman, DhanasekaranJeong, WoonyoungSong, WooseokAn, Ki-SeokJung, Jongwan
DOI
10.1039/c8ra03398f
발행일
2018
유형
Article
저널명
RSC Advances
8
45
페이지
25514 ~ 25518