Design of a 9.8fJ/conv 0.25mW 12-bit CMOS Fully Analog Cascaded-SAR ADC without a Track-and-Hold Amplifier

초록

This paper describes a novel successive approximation register (SAR) analog-To-digital converter (ADC) that eliminates the burden on the track and hold amplifier (THA). In a conventional pipelined-SAR ADC structure, the THA tracks the analog input signal and holds the input voltage. Therefore, as the sampling rate or resolution increases, the bandwidth of THA becomes higher. As the supply voltage decreases, designing a high-performance THA with a wide output voltage range, high DC gain, and a wide bandwidth becomes increasingly difficult. This issue arises due to the SAR structure employed in the conventional pipelined-SAR ADC. This paper proposes a novel cascaded-SAR ADC that applies the residue voltage generation technique, aiming to alleviate the burden on THA. This approach enables the design of high-resolution and low-power ADCs even at low supply voltages. A prototype chip has been fabricated with a Samsung 28nm process at 1.8V power supply. The proposed ADC operates at 12-bit resolution and a speed of 25MSps, which has a FOM performance of 9.8fJ/conv at 0.25mW. © 2026 IEEE.

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