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초록

This paper presents a low-power single-slope analog-to-digital converter (SS-ADC) that uses two comparators of the same structure to predict when a comparator flips. One of the comparators, a replica comparator, uses only half the bias current compared to the main comparator, causing the output of the comparator to flip early. By predicting the flipping time of the comparator in advance, power-gating techniques can be applied, resulting in reduced dynamic power consumption. The proposed 11-bit SS-ADC is fabricated using a 28-nm standard process, considering a resolution of 320 × 240 and an operating frame rate of 133 frames per second. Measurement results demonstrate that the power consumption of the proposed SS-ADC has decreased by approximately 17.6%. The total power consumption per column is 4.8 μW, and the figure of merit is 76.4 fJ/conversion step.

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