Radiation-Hardened 20T SRAM with Read and Write Optimization for Space Applications

Abstract

With continued CMOS scaling, transistor miniaturization has significantly raised SRAM integration density while lowering the critical charge (Qc), increasing cell vulnerability to spaceborne high-energy particles. Single-event upset (SEU) and especially single-event multiple node upsets (SEMNU) due to charge sharing present major reliability challenges. To overcome these issues, this study introduces a radiation-hardened 20T SRAM cell with read/write optimization (RWO-20T) designed for space applications. Benchmarking against hardened cells RH14T, RHSCC16T, S8P8N16T, and CC18T reveals that RWO-20T delivers superior read static noise margin (RSNM), increased word-line write trip voltage (WWTV), and faster read and write access times. Although the higher transistor count incurs some area overhead and slightly lowers the hold static noise margin (HSNM), RWO-20T achieves improved recovery rates for dual-node upsets (DNU) and triple-node upsets (TNU) under SEMNU conditions. The circuits were simulated in a 90 nm CMOS process and operated at 1 V.