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저전력, 고속 동작용 Successive Approximation Register (SAR) 로직 회로
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김수연 | - |
| dc.contributor.author | 김지원 | - |
| dc.date.accessioned | 2025-09-09T10:00:55Z | - |
| dc.date.available | 2025-09-09T10:00:55Z | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/61344 | - |
| dc.description.abstract | 본 발명은 제안하는 Successive Approximation Register (SAR) 로직을 이용함으로써 Sample and Hold Amplifier와 Residue Amplifier에 사용되는 Amplifier의 설계사양을 낮추어 저전력 고속 동작이 가능한 Analog-to-Digital Converter (ADC)를 설계하는 기술에 관련된 발명이다. | - |
| dc.title | 저전력, 고속 동작용 Successive Approximation Register (SAR) 로직 회로 | - |
| dc.title.alternative | Low-power and high-speed Successive Approximation Register circuit | - |
| dc.type | Patent | - |
| dc.publisher.location | 대한민국 | - |
| dc.contributor.assignee | 동국대학교산학협력단 | - |
| dc.date.application | 2023-07-10 | - |
| dc.date.registration | 2025-02-05 | - |
| dc.type.iprs | 특허 | - |
| dc.identifier.patentRegistrationNumber | 10-2765881 | - |
| dc.identifier.patentApplicationNumber | 10-2023-0088977 | - |
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Related Researcher
- Kim, Soo Youn
- College of Advanced Convergence Engineering (Division of System Semiconductor)