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클럭 및 데이터 복원 회로
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 변상진 | - |
| dc.date.accessioned | 2025-09-09T07:05:57Z | - |
| dc.date.available | 2025-09-09T07:05:57Z | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/59759 | - |
| dc.title | 클럭 및 데이터 복원 회로 | - |
| dc.title.alternative | clock and data recovery circuit | - |
| dc.type | Patent | - |
| dc.publisher.location | 대한민국 | - |
| dc.contributor.assignee | 동국대학교산학협력단 | - |
| dc.date.application | 2016-04-27 | - |
| dc.date.registration | 2017-07-04 | - |
| dc.type.iprs | 특허 | - |
| dc.identifier.patentRegistrationNumber | 10-1756098 | - |
| dc.identifier.patentApplicationNumber | 10-2016-0051512 | - |
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Related Researcher
- Byun, Sangjin
- College of Engineering (Department of Electronics and Electrical Engineering)