Custom Design Experiments for Semiconductor Package Optimization

Abstract

The design of memory semiconductors involves satisfying various customer demands and rapid provision of high-quality products; therefore, manufacturers have developed high-quality memory semiconductors using various technological elements to ensure their performance, reliability, and operation in various environments. Major quality aspects, such as warpage, stress, and strain, have different effects. Through experimental investigations, appropriate technological elements are selected using different technological elements (thickness and materials) to deliver the quality desired by customers. Experimental investigations may, however, delay product deliveries and incur considerable costs. This study proposes a new design method to overcome these limitations and determine optimal solutions based on the prepared technological elements for the quality desired by customers. The proposed method differs from traditional optimization methods in that it provides multiple solutions that satisfy the customer's requirements. Traditional experimental designs that use orthogonal arrays fail to reflect the various constraints involved in memory semiconductor designs. We, therefore, aimed to solve this problem by applying an analysis methodology for a mixture of experimental designs based on orthogonal arrays using the coordinate exchange algorithm. A desirability function was, furthermore, used to assess the satisfaction of multiple quality characteristics (warpage, stress, strain), through which optimal packaging conditions were confirmed at approximately 12.5% of the total combination level. The results of this study are expected to improve the optimization and efficiency of semiconductor packaging processes.