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Boosting non-volatile memory performance with exhalative annealing: A novel approach to low-temperature crystallization of hafnia based ferroelectric

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dc.contributor.authorLee, Yunseong-
dc.contributor.authorKim, Un Jeong-
dc.contributor.authorKim, Kihong-
dc.contributor.authorYun, Dong-Jin-
dc.contributor.authorChoe, Duk-hyun-
dc.contributor.authorYoo, Sijung-
dc.contributor.authorLee, Hyun Jae-
dc.contributor.authorNam, Seung-Geol-
dc.contributor.authorJo, Sanghyun-
dc.contributor.authorPark, Yoonsang-
dc.contributor.authorKim, Donghoon-
dc.contributor.authorKim, Dongmin-
dc.contributor.authorKim, Haeryong-
dc.contributor.authorShin, Keunwook-
dc.contributor.authorNahm, Sahn-
dc.contributor.authorHeo, Jinseong-
dc.date.accessioned2024-12-09T07:00:13Z-
dc.date.available2024-12-09T07:00:13Z-
dc.date.issued2024-12-
dc.identifier.issn2588-8420-
dc.identifier.issn2588-8420-
dc.identifier.urihttps://scholarworks.dongguk.edu/handle/sw.dongguk/56317-
dc.description.abstractIn this study, we propose a CMOS-compatible exhalative annealing (EA) method that can significantly reduce the annealing temperature of Zr-doped hafnia-based ferroelectrics (HZO). Compared to the conventional rapid thermal annealing (RTA) process, our EA process reduces the crystallization temperature (Tcryst) of HZO films across all thickness ranges (5–10 nm). In particular, a 5 nm-thick HZO film, which is ideal for future 3D semiconductor devices, exhibited a 50 % reduction in Tcryst from 500 °C to 250 °C. X-ray photoelectron spectroscopy (XPS) analysis reveals that the EA method reduces both residual carbon and oxygen vacancy concentrations. High-resolution transmission electron microscopy (HRTEM) confirmed a significant reduction in interfacial mixing between HZO and the electrodes. Capacitors made of Molybdenum (Mo) electrode/HZO/Mo electrode structure annealed using EA at 250 °C exhibited 2 orders of magnitude reduced leakage current at 3 MV cm−1, along with robust ferroelectric properties (2Pr and 2Ec values of 36.7 μC cm−2 and 2.38 MV cm−1, respectively). Implementing our method to ferroelectric field effect transistors (FeFETs) on a wafer scale resulted in a 33 % increase in their memory window. The CMOS-compatible EA method is effective for producing ferroelectric field-effect transistors on a wafer scale and is well suited for the fabrication of next-generation hafnia-based ferroelectric nonvolatile memory. EA holds great promise for developing future semiconductor devices due to its industry-friendly process and minimal thermal damage. © 2024 Elsevier Ltd-
dc.format.extent8-
dc.language영어-
dc.language.isoENG-
dc.publisherElsevier Ltd-
dc.titleBoosting non-volatile memory performance with exhalative annealing: A novel approach to low-temperature crystallization of hafnia based ferroelectric-
dc.typeArticle-
dc.publisher.location네델란드-
dc.identifier.doi10.1016/j.mtnano.2024.100546-
dc.identifier.scopusid2-s2.0-85209768293-
dc.identifier.wosid001396014200001-
dc.identifier.bibliographicCitationMaterials Today Nano, v.28, pp 1 - 8-
dc.citation.titleMaterials Today Nano-
dc.citation.volume28-
dc.citation.startPage1-
dc.citation.endPage8-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaScience & Technology - Other Topics-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalWebOfScienceCategoryNanoscience & Nanotechnology-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.subject.keywordPlusHF0.5ZR0.5O2 THIN-FILMS-
dc.subject.keywordPlusPHASE-TRANSITION-
dc.subject.keywordPlusOXYGEN VACANCIES-
dc.subject.keywordPlusDEPENDENCE-
dc.subject.keywordPlusTHICKNESS-
dc.subject.keywordPlusBEHAVIOR-
dc.subject.keywordPlusPLASMA-
dc.subject.keywordPlusHFO2-
dc.subject.keywordPlusZRO2-
dc.subject.keywordAuthorAtomic layer deposition-
dc.subject.keywordAuthorExhalative annealing-
dc.subject.keywordAuthorFerroelectrics-
dc.subject.keywordAuthorHafnia-based material-
dc.subject.keywordAuthorLow-temperature annealing-
dc.subject.keywordAuthorThermal damage-
dc.subject.keywordAuthorWafer scale-
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