Reduction of Local Thermal Effects in FinFETs With a Heat-Path Design Methodology

Abstract

In this letter, we propose a heat-path design for releasing heat confined in FinFETs. Conductive material stacks consisting of metals and vias on silicon can be good heat paths that lower junction temperature. However, they also increase parasitic capacitance, leading to degraded circuit performance. Therefore, we analyzed the impact of various heat paths with different metal stacks and locations on junction temperature, power consumption, and oscillation frequency of ring oscillators. Measurements of the oscillators showed that the optimized heat-path design had a 24.9%-lower change in junction temperature and a 1.53% higher oscillation frequency compared to a conventional layout. Furthermore, from thermally aware-compact model simulation results, we show that the proposed heat-path methodology can be more effective with the FinFET process than with the planar CMOS process.