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VHDL및 논리합성을 이용한 MPEG-2부호기 VLC모듈설계
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 원치선 | - |
| dc.date.accessioned | 2024-10-30T04:42:09Z | - |
| dc.date.available | 2024-10-30T04:42:09Z | - |
| dc.date.issued | 1996-11-23 | - |
| dc.identifier.uri | https://scholarworks.dongguk.edu/handle/sw.dongguk/40725 | - |
| dc.title | VHDL및 논리합성을 이용한 MPEG-2부호기 VLC모듈설계 | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | 추계종합학술대회 | - |
| dc.citation.conferencePlace | 대한민국 | - |
| dc.citation.conferencePlace | 서울 | - |
| dc.citation.conferenceDate | 1996-11-23 | - |
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