Analysis and Design of a 970-MHz, 108-Stage CMOS Ambient RF Energy Harvester With-36.5-dBm Input Power Sensitivity

Abstract

This article presents an analysis and design of a 970-MHz, 108-stage CMOS ambient radio frequency (RF) energy harvester (RFEH) with $-$ 36.5-dBm input power sensitivity. We have newly presented the transient analysis as well as the steady-state analysis of the RFEH to derive the closed form equations of the input power sensitivity, the passive amplification gain and the charging time. Instead of using the power conversion efficiency (PCE), we have newly defined the energy conver-sion efficiency (ECE) and proposed to use the charging time for the design optimization since we have adopted the on/off power management technique to enhance the input power sensitivity of the RFEH. The prototype RFEH has been implemented in a 28-nm 1P11M CMOS process, and the active die area is 0.025 mm(2 ). The measured input power sensitivity is as high as -36.5 dBm at 970 MHz, when the output dc voltage is 1.0 V. The measured initial charging time from 0.08 to 1.0 V is 8.5 s, and the recharging time from 0.89 to 1.0 V is 3.9 s when the storage capacitance is 1 nF. These results show good agreement with the predicted values by the derived equations.