Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line

Abstract

This brief presents a delay-locked-loop-based Gaussian frequency-shift keying (FSK) demodulator using a multiple-IF-period delay line. Theoretical analysis of the bit error rate (BER) performance is developed. The analysis result implies that the BER can be improved when a multiple-IF-period delay line is used instead of a single-IF-period delay line. To verify the analysis, a prototype chip was fabricated in a 0.11-mu m CMOS process. When a binary Gaussian FSK (GFSK) signal carries 1-Mb/s data on a 3-MHz center frequency with a 160-kHz frequency deviation, the minimum required signal-to-noise ratio for 0.1% BER is reduced from 17.5 to 12.5 dB when a triple-IF-period delay line is used instead of a single-IF-period delay line. The implemented GFSK demodulator consumes 0.8 mA from a 1.2-V supply voltage.