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SCISCIESCOPUS
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

Byun, Sangjin; Son, Chung Hwan; Hwang, Jongil; Min, Byung-Hun; Park, Mun-Yang; Yu, Hyun-Kyu

ArticleIssue Date2013CitationIET CIRCUITS DEVICES & SYSTEMS, v.7, no.3, pp 159 - 168PublisherINST ENGINEERING TECHNOLOGY-IET
SCIESCOPUSKCI
A 82.5% Power Efficiency at 1.2 mW Buck Converter with Sleep Controlopen access

Son, Chung Hwan; Byun, Sangjin

ArticleIssue Date2016CitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.6, pp 842 - 846PublisherIEEK PUBLICATION CENTER
SCISCIESCOPUS
On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors

Son, Chung Hwan; Byun, Sangjin

ArticleIssue Date2017CitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.7, pp 757 - 761PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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